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Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates
http://hdl.handle.net/10131/00011463
http://hdl.handle.net/10131/00011463f8dacb40-b2d7-45ef-a793-c4b855165d3b
名前 / ファイル | ライセンス | アクション |
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Nishimoto2015IEEE_final.pdf (663.5 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2018-01-24 | |||||
タイトル | ||||||
タイトル | Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Nishimoto, Shohei
× Nishimoto, Shohei× Yamanashi, Yuki× Yoshikawa, Nobuyuki |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 25, 号 3, p. 1301405, 発行日 2015-06 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 15582515 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2014.2387251 | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers |