{"created":"2023-06-20T15:12:05.318053+00:00","id":8789,"links":{},"metadata":{"_buckets":{"deposit":"32e39138-541a-48f7-b979-ac4aaba1499f"},"_deposit":{"created_by":3,"id":"8789","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8789"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00008789","sets":["495:496"]},"author_link":["33490","33488","19078"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2015-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicPageStart":"1301405","bibliographicVolumeNumber":"25","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.","subitem_description_type":"Abstract"}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers "}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TASC.2014.2387251","subitem_relation_type_select":"DOI"}}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"15582515","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Nishimoto, Shohei"}],"nameIdentifiers":[{"nameIdentifier":"33488","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yamanashi, Yuki"}],"nameIdentifiers":[{"nameIdentifier":"19078","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70467059","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]},{"creatorNames":[{"creatorName":"Yoshikawa, Nobuyuki"}],"nameIdentifiers":[{"nameIdentifier":"33490","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-01-24"}],"displaytype":"detail","filename":"Nishimoto2015IEEE_final.pdf","filesize":[{"value":"663.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"Nishimoto2015IEEE_final.pdf","url":"https://ynu.repo.nii.ac.jp/record/8789/files/Nishimoto2015IEEE_final.pdf"},"version_id":"40b6d5cb-d5f9-48e6-b2a8-e276176cf1b8"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates"}]},"item_type_id":"2","owner":"3","path":["496"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-01-24"},"publish_date":"2018-01-24","publish_status":"0","recid":"8789","relation_version_is_last":true,"title":["Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-06-20T20:03:13.832060+00:00"}