@article{oai:ynu.repo.nii.ac.jp:00008789,
 author = {Nishimoto, Shohei and Yamanashi, Yuki and Yoshikawa, Nobuyuki},
 issue = {3},
 journal = {IEEE Transactions on Applied Superconductivity},
 month = {Jun},
 note = {In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.},
 title = {Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates},
 volume = {25},
 year = {2015}
}