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20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits
http://hdl.handle.net/10131/910
http://hdl.handle.net/10131/9104bd6bf68-76bb-4e32-bd84-1866a2e2b16e
名前 / ファイル | ライセンス | アクション |
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ISI-000229765300046-01.pdf (616.5 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2007-06-07 | |||||
タイトル | ||||||
タイトル | 20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Adder, asynchronous system, bit-serial architecture, data-driven self-timing, handshaking, SFQ circuit | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Ito, M.
× Ito, M.× Kawasaki, K.× Yoshikawa, Nobuyuki× Fujimaki, A.× Terai, H.× Yorozu, S. |
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著者(ヨミ) | ||||||
識別子Scheme | WEKO | |||||
識別子 | 15641 | |||||
姓名 | ヨシカワ, ノブユキ | |||||
著者別名 | ||||||
識別子Scheme | WEKO | |||||
識別子 | 15642 | |||||
姓名 | 吉川, 信行 | |||||
著者所属 | ||||||
Yokohama Natl Univ, Dept Elect & Comp Engn, Yokohama, Kanagawa 2408501, Japan | ||||||
著者所属 | ||||||
Nagoya Univ, Dept Quantum Engn, Nagoya, Aichi 4648603, Japan | ||||||
著者所属 | ||||||
Natl Inst Informat & Commun Technol, Kobe, Hyogo 6512492, Japan | ||||||
著者所属 | ||||||
Supercond Res Lab, Int Supercond Technol Ctr, Tsu | ||||||
著者所属 | ||||||
横浜国立大学 工学研究院 知的構造の創生 | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Synchronous design is generally used in SFQ digital systems at present. In large-scale SFQ digital systems, however, the introduction of asynchronous design is required due to the large clock skew in the clock distribution network and complexity in the timing design at high clock rate. We have proposed a hierarchical design approach using asynchronous SFQ circuits with handshaking protocol for asynchronous data transfer. In our asynchronous approach, each circuit module is designed based on a data driven self-timed (DDST) architecture. A handshaking protocol is also used to ensure the logical ordering in data communication between the modules, where we have adopted bit-serial architecture to reduce the communication costs in handshaking. One issues in the bit-serial handshaking (BSHS) system is the synchronization of the input data when the module has multiple input ports. In this study, we have designed an SFQ BSHS system with multiple input ports, where Muller C-elements is used to synchronize the multiple input data. We have designed and implemented a BSHS half adder using NEC 2.5 kA/cm(2) Nb standard process to demonstrate asynchronous addition of two input data at high speed. We have successfully confirmed its correct operation at about 20 GHz. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 15, 号 2, Part 1, p. 255-258, 発行日 2005-06 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 10518223 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10791666 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/TASC.2005.849773 | |||||
権利 | ||||||
権利情報 | (c)2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers |