{"created":"2023-06-20T15:07:57.466429+00:00","id":3651,"links":{},"metadata":{"_buckets":{"deposit":"8e928b3b-e0d2-42b0-a573-8be3463b995d"},"_deposit":{"created_by":3,"id":"3651","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"3651"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00003651","sets":["495:496"]},"author_link":["15638","15641","15639","15637","15640","15642","15636","15635"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2005-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2, Part 1","bibliographicPageEnd":"258","bibliographicPageStart":"255","bibliographicVolumeNumber":"15","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_17":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Synchronous design is generally used in SFQ digital systems at present. In large-scale SFQ digital systems, however, the introduction of asynchronous design is required due to the large clock skew in the clock distribution network and complexity in the timing design at high clock rate. We have proposed a hierarchical design approach using asynchronous SFQ circuits with handshaking protocol for asynchronous data transfer. In our asynchronous approach, each circuit module is designed based on a data driven self-timed (DDST) architecture. A handshaking protocol is also used to ensure the logical ordering in data communication between the modules, where we have adopted bit-serial architecture to reduce the communication costs in handshaking. One issues in the bit-serial handshaking (BSHS) system is the synchronization of the input data when the module has multiple input ports. In this study, we have designed an SFQ BSHS system with multiple input ports, where Muller C-elements is used to synchronize the multiple input data. We have designed and implemented a BSHS half adder using NEC 2.5 kA/cm(2) Nb standard process to demonstrate asynchronous addition of two input data at high speed. We have successfully confirmed its correct operation at about 20 GHz.","subitem_description_type":"Abstract"}]},"item_2_full_name_2":{"attribute_name":"著者(ヨミ)","attribute_value_mlt":[{"nameIdentifiers":[{}],"names":[{"name":"ヨシカワ, ノブユキ"}]}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{}],"names":[{}]}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers"}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1109/TASC.2005.849773","subitem_relation_type_select":"DOI"}}]},"item_2_rights_14":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"(c)2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"10518223","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Yokohama Natl Univ, Dept Elect & Comp Engn, Yokohama, Kanagawa 2408501, Japan"},{"subitem_text_value":"Nagoya Univ, Dept Quantum Engn, Nagoya, Aichi 4648603, Japan"},{"subitem_text_value":"Natl Inst Informat & Commun Technol, Kobe, Hyogo 6512492, Japan"},{"subitem_text_value":"Supercond Res Lab, Int Supercond Technol Ctr, Tsu"},{"subitem_text_value":"横浜国立大学　工学研究院　知的構造の創生"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ito, M."}],"nameIdentifiers":[{"nameIdentifier":"15635","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Kawasaki, K."}],"nameIdentifiers":[{"nameIdentifier":"15636","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yoshikawa, Nobuyuki"}],"nameIdentifiers":[{"nameIdentifier":"15637","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Fujimaki, A."}],"nameIdentifiers":[{"nameIdentifier":"15638","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Terai, H."}],"nameIdentifiers":[{"nameIdentifier":"15639","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yorozu, S."}],"nameIdentifiers":[{"nameIdentifier":"15640","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-09-16"}],"displaytype":"detail","filename":"ISI-000229765300046-01.pdf","filesize":[{"value":"616.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"ISI-000229765300046-01.pdf","url":"https://ynu.repo.nii.ac.jp/record/3651/files/ISI-000229765300046-01.pdf"},"version_id":"9b7599c7-248d-433c-9add-701f0463a085"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Adder","subitem_subject_scheme":"Other"},{"subitem_subject":"asynchronous system","subitem_subject_scheme":"Other"},{"subitem_subject":"bit-serial architecture","subitem_subject_scheme":"Other"},{"subitem_subject":"data-driven self-timing","subitem_subject_scheme":"Other"},{"subitem_subject":"handshaking","subitem_subject_scheme":"Other"},{"subitem_subject":"SFQ circuit","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits"}]},"item_type_id":"2","owner":"3","path":["496"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-06-07"},"publish_date":"2007-06-07","publish_status":"0","recid":"3651","relation_version_is_last":true,"title":["20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-06-20T21:43:53.815234+00:00"}