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  1. 08 先端科学高等研究院
  2. 8-1 学術雑誌論文
  1. 09 総合学術高等研究院
  2. 9-1 学術雑誌論文
  1. 05 工学研究院・理工学府・理工学部
  2. 5-1 学術雑誌論文

A binary neural computing unit with programmable gate using SFQ and CMOS hybrid circuit

http://hdl.handle.net/10131/0002000913
http://hdl.handle.net/10131/0002000913
332def74-a4c4-4602-a327-02f251a6a582
名前 / ファイル ライセンス アクション
Li2024SUST.pdf Li2024SUST.pdf (636 KB)
アイテムタイプ 学術雑誌論文 / Journal Article(1)
公開日 2024-05-16
タイトル
タイトル A binary neural computing unit with programmable gate using SFQ and CMOS hybrid circuit
言語 en
言語
言語 eng
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
アクセス権
アクセス権 open access
アクセス権URI http://purl.org/coar/access_right/c_abf2
著者 Li, Zongyuan

× Li, Zongyuan

en Li, Zongyuan
Department of Electrical and Computer Engineering, Yokohama National University

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Shen, Hongxiang

× Shen, Hongxiang

en Shen, Hongxiang
Institute of Advanced Sciences, Yokohama National University

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Yoshikawa, Nobuyuki

× Yoshikawa, Nobuyuki

e-Rad_Researcher 70202398

en Yoshikawa, Nobuyuki
Department of Electrical and Computer Engineering, Yokohama National University
Institute of Advanced Sciences, Yokohama National University
Institute for Multidisciplinary Sciences, Yokohama National University

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Yamanashi, Yuki

× Yamanashi, Yuki

e-Rad_Researcher 70467059

en Yamanashi, Yuki
Department of Electrical and Computer Engineering, Yokohama National University
Institute of Advanced Sciences, Yokohama National University
Institute for Multidisciplinary Sciences, Yokohama National University

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抄録
内容記述タイプ Abstract
内容記述 Superconducting neural networks hold significant potential for future applications such as natural language processing and image recognition. To this end, we propose a binary neural computing unit implemented using a hybrid circuit of cryogenic CMOS and superconducting technologies. It offers two main advantages: firstly, we utilize current-mode computations for neural unit weight calculations, significantly reducing the unit's footprint and enabling the potential for higher integration in the future. Secondly, all computations are performed in a low-temperature environment, which implies the possibility of on-chip learning in superconducting neural networks and the potential for achieving faster training rates in the future. We fabricated the chip using Nb 1 kA cm−2 process (1KP) technology and experimentally verified the correctness of the circuit logic. The margins for various control parameters of the circuit are approximately around 30%, and the superconducting circuit power consumption is estimated to be around 4 microwatts.
言語 en
書誌情報 en : Superconductor Science and Technology

巻 37, 号 6, ページ数 6, 発行日 2024-05-13
ISSN
収録物識別子タイプ EISSN
収録物識別子 13616668
書誌レコードID
収録物識別子タイプ NCID
収録物識別子 AA1247275X
DOI
関連タイプ isVersionOf
識別子タイプ DOI
関連識別子 https://doi.org/10.1088/1361-6668/ad44e2
権利
権利情報Resource https://publishingsupport.iopscience.iop.org/accepted-manuscripts/
権利情報 This Accepted Manuscript is available for reuse under a CC BY-NC-ND licence after the 12 month embargo period provided that all the terms of the licence are adhered to.
言語 en
著者版フラグ
出版タイプ AM
出版タイプResource http://purl.org/coar/version/c_ab4af688f83e57aa
出版者
出版者 IOP Publishing
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