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Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits
http://hdl.handle.net/10131/00014758
http://hdl.handle.net/10131/0001475835964641-a48e-437f-98d6-5df56f290a20
名前 / ファイル | ライセンス | アクション |
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TAS-2022-0023_AM.pdf (3.8 MB)
Download is available from 2024/7/26.
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2022-09-01 | |||||
タイトル | ||||||
タイトル | Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Power transmission lines, Logic gates, Integrated circuit interconnections, Superconducting transmission lines, Resistance, Reflection, Integrated circuit modeling, error statistics, logic gates, parametric oscillators, superconducting logic circuits, gate-to-gate interconnection, AQFP logic circuits, reflection effect, long transmission line, AQFP gates, interconnection length, transmission line effects, long gate-to-gate interconnections, adiabatic quantum-flux-parametron logic circuits, energy-efficient superconductor logic family, logic gates, bit error rates, Adiabatic logic, bit error rate (BER), damping resistance, interconnection, quantum flux parametron (QFP), superconductor integrated circuit, transmission line | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Kazuhito, Asai
× Kazuhito, Asai× Naoki, Takeuchi× Hideo, Suzuki× Yuki, Yamanashi× Nobuyuki, Yoshikawa |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University & Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family that utilizes adiabatic switching of logic gates. At present, a pure inductance is used to model a gate-to-gate interconnection in AQFP logic circuits. However, it is necessary to consider the transmission line effects when the interconnection length becomes long to take into account the propagation delay. This study investigated the transmission line effects of a long gate-to-gate interconnection in AQFP logic circuits. We observed reflection effects in a long transmission line between AQFP gates. These effects induced errors when the interconnection length exceeded several hundred micrometers. We adopted a damping resistance to stabilize the reflection effect to realize an error-free long gate-to-gate interconnection. The circuit simulations confirmed that a damping resistance connected in parallel to the transmission line effectively stabilizes the reflection effect, enabling an interconnection length that is longer than 1 mm. We fabricated AQFP buffer chains that included a long transmission line with and without a parallel damping resistance, and measured their bit error rates. The results showed that the parallel damping resistance effectively improves the bit error rate at high frequencies. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 32, 号 7, 発行日 2022-07-27 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 15582515 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10791666 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2022.3183496 | |||||
権利 | ||||||
権利情報 | © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers | |||||
関係URI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/TASC.2022.3183496 | |||||
関連名称 | https://doi.org/10.1109/TASC.2022.3183496 |