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Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory
http://hdl.handle.net/10131/00014757
http://hdl.handle.net/10131/00014757ff98914c-01d0-4356-a1e9-81abab7b13a5
名前 / ファイル | ライセンス | アクション |
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IEEE_TAS_Takahashi_AM.pdf (7.5 MB)
Download is available from 2024/7/5.
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2022-09-01 | |||||
タイトル | ||||||
タイトル | Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Field programmable gate arrays, Power demand, Josephson junctions, Clocks, Switching circuits, Superconducting logic circuits, Logic gates, field programmable gate arrays, integrated logic circuits, logic circuits, low-power electronics, parametric oscillators, superconducting logic circuits, AQFP circuits, AQFP buffer chains, low-power memory, switch blocks, logic functions, design flexibility, all-AQFP FPGA, superconducting FPGAs, superconducting field-programmable gate array, adiabatic quantum-flux-parametron logic, future energy-efficient, high- performance information processing systems, low power consumption, adiabatic switching, high-performance field-programmable gate array, energy consumption, logic blocks, connection blocks, Adiabatic logic, field-programmable gate array (FPGA), Josephson-integrated circuits, quantum flux parametron (QFP), superconducting-integrated circuits | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Daichi, Takahashi
× Daichi, Takahashi× Naoki, Takeuchi× Yuki, Yamanashi× Nobuyuki, Yoshikawa |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University & Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority, and, and or functions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 32, 号 7, 発行日 2022-07-06 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 15582515 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10791666 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2022.3188865 | |||||
権利 | ||||||
権利情報 | © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers | |||||
関係URI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/TASC.2022.3188865 | |||||
関連名称 | https://doi.org/10.1109/TASC.2022.3188865 |