{"created":"2023-06-20T15:14:46.616261+00:00","id":12107,"links":{},"metadata":{"_buckets":{"deposit":"bd44bf6a-1827-4307-8359-572f98414a2a"},"_deposit":{"created_by":3,"id":"12107","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"12107"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00012107","sets":["1006:1009"]},"author_link":["19078","35237","35701","43140"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"32","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority, and, and or functions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.","subitem_description_type":"Abstract"}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers"}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TASC.2022.3188865","subitem_relation_type_select":"DOI"}}]},"item_2_relation_44":{"attribute_name":"関係URI","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"https://doi.org/10.1109/TASC.2022.3188865"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/TASC.2022.3188865","subitem_relation_type_select":"DOI"}}]},"item_2_rights_14":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"© 2022 IEEE.  Personal use of this material is permitted.  Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_2_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"15582515","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Institute of Advanced Sciences, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Institute of Advanced Sciences, Yokohama National University & Department of Electrical and Computer Engineering, Yokohama National University"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Daichi, Takahashi"}],"nameIdentifiers":[{"nameIdentifier":"43140","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Naoki, Takeuchi"}],"nameIdentifiers":[{"nameIdentifier":"35701","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"00746472","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=00746472"}]},{"creatorNames":[{"creatorName":"Yuki, Yamanashi"}],"nameIdentifiers":[{"nameIdentifier":"19078","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70467059","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]},{"creatorNames":[{"creatorName":"Nobuyuki, Yoshikawa"}],"nameIdentifiers":[{"nameIdentifier":"35237","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70202398","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70202398"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2024-07-06"}],"displaytype":"detail","filename":"IEEE_TAS_Takahashi_AM.pdf","filesize":[{"value":"7.5 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"IEEE_TAS_Takahashi_AM.pdf","url":"https://ynu.repo.nii.ac.jp/record/12107/files/IEEE_TAS_Takahashi_AM.pdf"},"version_id":"4cc10e82-beb0-4590-a704-5712c639d9ca"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Field programmable gate arrays","subitem_subject_scheme":"Other"},{"subitem_subject":"Power demand","subitem_subject_scheme":"Other"},{"subitem_subject":"Josephson junctions","subitem_subject_scheme":"Other"},{"subitem_subject":"Clocks","subitem_subject_scheme":"Other"},{"subitem_subject":"Switching circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"Superconducting logic circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"Logic gates","subitem_subject_scheme":"Other"},{"subitem_subject":"field programmable gate arrays","subitem_subject_scheme":"Other"},{"subitem_subject":"integrated logic circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"logic circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"low-power electronics","subitem_subject_scheme":"Other"},{"subitem_subject":"parametric oscillators","subitem_subject_scheme":"Other"},{"subitem_subject":"superconducting logic circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"AQFP circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"AQFP buffer chains","subitem_subject_scheme":"Other"},{"subitem_subject":"low-power memory","subitem_subject_scheme":"Other"},{"subitem_subject":"switch blocks","subitem_subject_scheme":"Other"},{"subitem_subject":"logic functions","subitem_subject_scheme":"Other"},{"subitem_subject":"design flexibility","subitem_subject_scheme":"Other"},{"subitem_subject":"all-AQFP FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"superconducting FPGAs","subitem_subject_scheme":"Other"},{"subitem_subject":"superconducting field-programmable gate array","subitem_subject_scheme":"Other"},{"subitem_subject":"adiabatic quantum-flux-parametron logic","subitem_subject_scheme":"Other"},{"subitem_subject":"future energy-efficient","subitem_subject_scheme":"Other"},{"subitem_subject":"high- performance information processing systems","subitem_subject_scheme":"Other"},{"subitem_subject":"low power consumption","subitem_subject_scheme":"Other"},{"subitem_subject":"adiabatic switching","subitem_subject_scheme":"Other"},{"subitem_subject":"high-performance field-programmable gate array","subitem_subject_scheme":"Other"},{"subitem_subject":"energy consumption","subitem_subject_scheme":"Other"},{"subitem_subject":"logic blocks","subitem_subject_scheme":"Other"},{"subitem_subject":"connection blocks","subitem_subject_scheme":"Other"},{"subitem_subject":"Adiabatic logic","subitem_subject_scheme":"Other"},{"subitem_subject":"field-programmable gate array (FPGA)","subitem_subject_scheme":"Other"},{"subitem_subject":"Josephson-integrated circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"quantum flux parametron (QFP)","subitem_subject_scheme":"Other"},{"subitem_subject":"superconducting-integrated circuits","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory"}]},"item_type_id":"2","owner":"3","path":["1009"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-09-01"},"publish_date":"2022-09-01","publish_status":"0","recid":"12107","relation_version_is_last":true,"title":["Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-06-20T17:40:13.391789+00:00"}