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Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions
http://hdl.handle.net/10131/00012360
http://hdl.handle.net/10131/00012360c7a16735-e661-4204-98ec-6bff3023d6ef
名前 / ファイル | ライセンス | アクション |
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Yamanashi2019IEEE.pdf (735.6 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2019-04-15 | |||||
タイトル | ||||||
タイトル | Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Single-flux-quantum (SFQ) circuit, π-shifted Josephson junction, flip-flop | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Yamanashi, Yuki
× Yamanashi, Yuki× Nakaishi, Sotaro× Yoshikawa, Nobuyuki |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of intro-duction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The de-signed flip-flops and logic gates have wide operating margins, the dc bias margins of larger than ±30% and device parameter mar-gins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop com-posed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 29, 号 5, p. 1301805, 発行日 2019-08 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 10518223 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11946236 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2019.2904700 | |||||
権利 | ||||||
権利情報 | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | IEEE |