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Improvement of Operation Speed of LR-Biased Low-Power Single-Flux Quantum Circuits by Introduction of Dynamic Resetting of Bias Currents
http://hdl.handle.net/10131/00011461
http://hdl.handle.net/10131/00011461bf9b59e8-faf7-46a6-a4db-bac06e8dc7b3
名前 / ファイル | ライセンス | アクション |
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Tsutsumi2016IEEE_final.pdf (876.0 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2018-01-24 | |||||
タイトル | ||||||
タイトル | Improvement of Operation Speed of LR-Biased Low-Power Single-Flux Quantum Circuits by Introduction of Dynamic Resetting of Bias Currents | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Tsutsumi, Ryuta
× Tsutsumi, Ryuta× Sato, Koji× Yamanashi, Yuki |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We propose a new inductive- and resistive- (LR) biased low-power single-flux quantum (SFQ) circuit that has a dynamic resetting mechanism of the bias current. Because the bias current returns to the initial state rapidly by switching of a Josephson junction in the bias circuit after circuit operation, the operating frequency of the LR-biased SFQ circuit can be improved. We simulated a Josephson transmission line (JTL) that employs the proposed biasing scheme and evaluated the bias current recovery time. Circuit simulation results show that the bias current recovery time of the proposed circuit is improved by 10-20% compared to that of the conventional LR-biased JTL. We have designed and measured a 10-stage JTL and an 8-bit concurrent-flow shift register (SR) with the proposed biasing scheme. We have experimentally demonstrated operation of the JTL with the bias margin of ±29.4% at the operating frequency of up to 70.4 GHz and operation of the 8-bit SR up to 12.3 GHz by the on-chip high-speed test. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 26, 号 8, p. 1301405, 発行日 2016-12 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 15582515 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2016.2598766 | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers |