{"created":"2023-06-20T15:12:05.884304+00:00","id":8799,"links":{},"metadata":{"_buckets":{"deposit":"c33064cd-5187-4424-a2a1-16bc72a12906"},"_deposit":{"created_by":3,"id":"8799","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8799"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00008799","sets":["495:496"]},"author_link":["33522","33523","19078"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicPageEnd":"834","bibliographicPageStart":"831","bibliographicVolumeNumber":"21","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Novel reconfigurable superconductive single flux quantum (SFQ) logic devices, the functions of which can be dynamically reconfigured by inputting control signals, have been investigated. The characteristics of single flux quantum circuits can be easily modulated by applying currents or magnetic fields because of the high sensitivity of superconductive circuits. We investigated several design approaches for the realization of dynamically reconfigurable SFQ logic devices. We employed direct current injection to the logic gate using a non-destructive read-out flip-flop. By changing the internal state of the non-destructive read-out flip-flop, the logic function can be dynamically reconfigured. We have designed and tested a dynamically reconfigurable Josephson transmission line (JTL)/delay flip-flop (DFF) circuit. The measured dc bias margin was 72.5-107.2%. Furthermore, we have demonstrated the operation of a variable bit-length shift register, composed of the dynamically reconfigurable JTL/DFF circuits. The investigated design approach can be applied to more sophisticated dynamically reconfigurable single flux quantum logic gates.","subitem_description_type":"Abstract"}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers "}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TASC.2010.2090856","subitem_relation_type_select":"DOI"}}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"15582515","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Interdisciplinary Research Center, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yamanashi, Yuki"}],"nameIdentifiers":[{"nameIdentifier":"19078","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70467059","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]},{"creatorNames":[{"creatorName":"Okawa, I."}],"nameIdentifiers":[{"nameIdentifier":"33522","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yoshikawa, N."}],"nameIdentifiers":[{"nameIdentifier":"33523","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-01"}],"displaytype":"detail","filename":"Yamanashi2011IEEE.pdf","filesize":[{"value":"480.8 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"Yamanashi2011IEEE.pdf","url":"https://ynu.repo.nii.ac.jp/record/8799/files/Yamanashi2011IEEE.pdf"},"version_id":"7a9f3317-ba8f-405f-bf3b-c6e7c06d1c36"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Gates","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Gates"}]},"item_type_id":"2","owner":"3","path":["496"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-02-01"},"publish_date":"2018-02-01","publish_status":"0","recid":"8799","relation_version_is_last":true,"title":["Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Gates"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-06-20T20:03:27.945764+00:00"}