{"created":"2023-06-20T15:12:05.794400+00:00","id":8797,"links":{},"metadata":{"_buckets":{"deposit":"f48f2ab8-c129-4669-a714-d62ee9624726"},"_deposit":{"created_by":3,"id":"8797","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8797"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00008797","sets":["495:496"]},"author_link":["33515","33517","33516"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2013-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicPageEnd":"1300904","bibliographicPageStart":"1300904","bibliographicVolumeNumber":"23","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2 Nb process, can be improved by 15% as compared with the conventional design at a frequency of 20 GHz by employing our novel design method.","subitem_description_type":"Abstract"}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers "}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TASC.2012.2234176","subitem_relation_type_select":"DOI"}}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"15582515","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"},{"subitem_text_value":"Department of Electrical and Computer Engineering, Yokohama National University"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Otsubo, Mikio"}],"nameIdentifiers":[{"nameIdentifier":"33515","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yamanashi, Yuki"}],"nameIdentifiers":[{"nameIdentifier":"33516","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yoshikawa, Nobuyuki"}],"nameIdentifiers":[{"nameIdentifier":"33517","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-01"}],"displaytype":"detail","filename":"Otsubo2013IEEE.pdf","filesize":[{"value":"491.0 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"Otsubo2013IEEE.pdf","url":"https://ynu.repo.nii.ac.jp/record/8797/files/Otsubo2013IEEE.pdf"},"version_id":"8b65fd9c-019a-4590-8a80-582455a798f4"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage"}]},"item_type_id":"2","owner":"3","path":["496"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-02-01"},"publish_date":"2018-02-01","publish_status":"0","recid":"8797","relation_version_is_last":true,"title":["Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-06-20T20:06:28.657813+00:00"}