@article{oai:ynu.repo.nii.ac.jp:00008785,
 author = {Yamanashi, Yuki and Nishimoto, Shohei and Yoshikawa, Nobuyuki},
 issue = {6},
 journal = {IEICE TRANSACTIONS on Electronics},
 month = {Jun},
 note = {A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.},
 pages = {692--696},
 title = {30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates},
 volume = {E99-C},
 year = {2016}
}