{"created":"2023-06-20T15:07:58.112256+00:00","id":3666,"links":{},"metadata":{"_buckets":{"deposit":"e7d2a95e-2f2e-4c08-ad81-976929150367"},"_deposit":{"created_by":3,"id":"3666","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"3666"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00003666","sets":["495:496"]},"author_link":["15728","15723","15727","15725","15722","15726","15724","15721"],"item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2005-09","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicPageEnd":"3820","bibliographicPageStart":"3814","bibliographicVolumeNumber":"15","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_17":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2 x 2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45 % fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of +/- 9.5%.","subitem_description_type":"Abstract"}]},"item_2_full_name_2":{"attribute_name":"著者(ヨミ)","attribute_value_mlt":[{"nameIdentifiers":[{}],"names":[{"name":"ヨシカワ, ノブユキ"}]}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{}],"names":[{}]}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers"}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1109/TASC.2005.847487","subitem_relation_type_select":"DOI"}}]},"item_2_rights_14":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"(c)2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"10518223","subitem_source_identifier_type":"ISSN"}]},"item_2_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Int Superconduct Technol Ctr, Superconduct Res Lab, Ibaraki 3058501, Japan"},{"subitem_text_value":"Nagoya Univ, Nagoya, Aichi 4648603, Japan"},{"subitem_text_value":"Natl Inst Informat & Commun Technol, Kobe, Hyogo 6512492, Japan"},{"subitem_text_value":"Yokohama Natl Univ, Yokohama, Kanagawa 2408501, Japan"},{"subitem_text_value":"横浜国立大学　工学研究院　知的構造の創生"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hashimoto, Y."}],"nameIdentifiers":[{"nameIdentifier":"15721","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yorozu, S."}],"nameIdentifiers":[{"nameIdentifier":"15722","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Kameda, Y."}],"nameIdentifiers":[{"nameIdentifier":"15723","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Fujimaki, A."}],"nameIdentifiers":[{"nameIdentifier":"15724","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Terai, H."}],"nameIdentifiers":[{"nameIdentifier":"15725","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yoshikawa, Nobuyuki"}],"nameIdentifiers":[{"nameIdentifier":"15726","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-09-16"}],"displaytype":"detail","filename":"ISI-000231858300003-01.pdf","filesize":[{"value":"1.2 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"ISI-000231858300003-01.pdf","url":"https://ynu.repo.nii.ac.jp/record/3666/files/ISI-000231858300003-01.pdf"},"version_id":"f88d79cc-3a63-40d3-8e07-57fc845794df"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"integrated circuit","subitem_subject_scheme":"Other"},{"subitem_subject":"interconnection","subitem_subject_scheme":"Other"},{"subitem_subject":"passive transmission line","subitem_subject_scheme":"Other"},{"subitem_subject":"single-flux-quantum (SFQ)","subitem_subject_scheme":"Other"},{"subitem_subject":"superconductor","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits"}]},"item_type_id":"2","owner":"3","path":["496"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-06-07"},"publish_date":"2007-06-07","publish_status":"0","recid":"3666","relation_version_is_last":true,"title":["Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-06-20T21:43:48.034193+00:00"}