{"created":"2023-06-20T15:14:47.832456+00:00","id":12142,"links":{},"metadata":{"_buckets":{"deposit":"79ca1f91-af0d-436c-9fa7-ea12a562567e"},"_deposit":{"created_by":3,"id":"12142","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"12142"},"status":"published"},"_oai":{"id":"oai:ynu.repo.nii.ac.jp:00012142","sets":["1006:1009"]},"author_link":["43243","43244","19078","35237"],"control_number":"12142","item_2_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2022-08-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"32","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Applied Superconductivity"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"We propose a compact single-flux-quantum (SFQ) lookup table (LUT) that uses CMOS decoder circuits for reconfiguration to improve scalability. Reconfiguration by external control currents. An n×n -bit LUT is composed of a two-dimensional array of memory cells and cryo-CMOS decoders. The memory cell at the target address is set to a logic “1” state when the corresponding x - and y -directional control currents are both applied from the CMOS decoders and is reset to logic “0” when a reset current is applied. Cryo-CMOS decoders are integrated with the SFQ LUT to reduce the number of control current lines (from 2 n +1 to 2log 2 n +2) from the room-temperature electronics for LUT reconfiguration. For demonstration, we designed and fabricated a 64-b SFQ LUT integrated with CMOS decoders using the AIST 2.5-kA/cm 2 Nb standard process and the Rohm 180-nm CMOS process. Experimental results confirm the correct functionality of the SFQ LUT reconfigured by the CMOS decoders. All operating SFQ memory cells in the experiment showed almost the same control current margins. The proposed reconfiguration method is scalable in terms of the number of interconnections and control current margins for SFQ memory cells.","subitem_description_type":"Abstract"}]},"item_2_publisher_35":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers"}]},"item_2_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TASC.2022.3191984","subitem_relation_type_select":"DOI"}}]},"item_2_relation_44":{"attribute_name":"関係URI","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"https://doi.org/10.1109/TASC.2022.3191984"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/TASC.2022.3191984","subitem_relation_type_select":"DOI"}}]},"item_2_rights_14":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"© 2022 IEEE.  Personal use of this material is permitted.  Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_2_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"15582515","subitem_source_identifier_type":"EISSN"}]},"item_2_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAffiliations":[{"affiliationNames":[{"affiliationName":"Department of Electrical and Computer Engineering, Yokohama National University","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"Yuki, Hironaka","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"43243","nameIdentifierScheme":"WEKO"}]},{"creatorAffiliations":[{"affiliationNames":[{"affiliationName":"Department of Electrical and Computer Engineering, Yokohama National University","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"Takuya, Hosoya","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"43244","nameIdentifierScheme":"WEKO"}]},{"creatorAffiliations":[{"affiliationNames":[{"affiliationName":"Department of Electrical and Computer Engineering, Yokohama National University & Institute of Advanced Sciences, Yokohama National University","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"Yuki, Yamanashi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"19078","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70467059","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]},{"creatorAffiliations":[{"affiliationNames":[{"affiliationName":"Department of Electrical and Computer Engineering, Yokohama National University","affiliationNameLang":"en"},{"affiliationName":"Institute of Advanced Sciences, Yokohama National University","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"Nobuyuki, Yoshikawa","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"35237","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"70202398","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=70202398"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2024-08-18"}],"displaytype":"detail","filename":"FINAL_VERSION.pdf","filesize":[{"value":"737.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"FINAL_VERSION.pdf","url":"https://ynu.repo.nii.ac.jp/record/12142/files/FINAL_VERSION.pdf"},"version_id":"d44c2d57-281d-446a-8456-06d96bc4b7d5"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Decoding , Table lookup , Transistors , Logic gates , Integrated circuit interconnections , Field programmable gate arrays , Standards","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS logic circuits , integrated circuit manufacture , logic design , superconducting integrated circuits , superconducting logic circuits , table lookup","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"y-directional control currents , reset current , cryo-CMOS decoders , SFQ LUT , control current lines , LUT reconfiguration , Rohm CMOS process","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"SFQ memory cells , control current margins , reconfiguration method , compact single-flux-quantum lookup table","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS decoder circuits , external control currents , n×n-bit LUT , memory cell , single-flux-quantum lookup table , two-dimensional array , x-directional control currents , size 180 nm","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Cryogenic memory , lookup table , memory cell , single-flux-quantum (SFQ) circuit","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration","subitem_title_language":"en"}]},"item_type_id":"2","owner":"3","path":["1009"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2022-10-03"},"publish_date":"2022-10-03","publish_status":"0","recid":"12142","relation_version_is_last":true,"title":["Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2024-02-19T02:11:53.601737+00:00"}