WEKO3
アイテム
{"_buckets": {"deposit": "a47c64e9-aad3-4e50-a01d-608bcec15de2"}, "_deposit": {"created_by": 3, "id": "9289", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "9289"}, "status": "published"}, "_oai": {"id": "oai:ynu.repo.nii.ac.jp:00009289", "sets": ["496"]}, "author_link": ["19078", "34414", "34412", "34415", "34413"], "item_2_biblio_info_8": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2018-08-28", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "10", "bibliographicPageEnd": "105003-7", "bibliographicPageStart": "105003-1", "bibliographicVolumeNumber": "31", "bibliographic_titles": [{"bibliographic_title": "Superconductor Science and Technology"}]}]}, "item_2_description_5": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π-shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π-shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π-shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and -shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0-π Josephson junctions.", "subitem_description_type": "Abstract"}]}, "item_2_publisher_35": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IOP Publishing"}]}, "item_2_relation_13": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "info:doi/10.1088/1361-6668/aad78d", "subitem_relation_type_select": "DOI"}}]}, "item_2_rights_14": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "© 2018 IOP Publishing Ltd. Original content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI."}]}, "item_2_source_id_11": {"attribute_name": "書誌レコードID", "attribute_value_mlt": [{"subitem_source_identifier": "AA10686810", "subitem_source_identifier_type": "NCID"}]}, "item_2_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "09532048", "subitem_source_identifier_type": "ISSN"}]}, "item_2_text_4": {"attribute_name": "著者所属", "attribute_value_mlt": [{"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": " Institute of Advanced Sciences, Yokohama National University"}, {"subitem_text_value": " Department of Electrical and Computer Engineering, Yokohama National University"}]}, "item_2_version_type_18": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Yamanashi, Yuki"}], "nameIdentifiers": [{"nameIdentifier": "19078", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "70467059", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]}, {"creatorNames": [{"creatorName": "Nakaishi, Sotaro"}], "nameIdentifiers": [{"nameIdentifier": "34412", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Sugiyama, Akira"}], "nameIdentifiers": [{"nameIdentifier": "34413", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Takeuchi, Naoki"}], "nameIdentifiers": [{"nameIdentifier": "34414", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yoshikawa, Nobuyuki"}], "nameIdentifiers": [{"nameIdentifier": "34415", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2018-08-20"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "yamanashi_P.pdf", "filesize": [{"value": "1.5 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_6", "mimetype": "application/pdf", "size": 1500000.0, "url": {"label": "yamanashi_P.pdf", "url": "https://ynu.repo.nii.ac.jp/record/9289/files/yamanashi_P.pdf"}, "version_id": "b6959756-4d2c-47ec-aeaf-53d470568bc4"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions"}]}, "item_type_id": "2", "owner": "3", "path": ["496"], "permalink_uri": "http://hdl.handle.net/10131/00011959", "pubdate": {"attribute_name": "公開日", "attribute_value": "2018-08-20"}, "publish_date": "2018-08-20", "publish_status": "0", "recid": "9289", "relation": {}, "relation_version_is_last": true, "title": ["Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions"], "weko_shared_id": 3}
Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions
http://hdl.handle.net/10131/00011959
http://hdl.handle.net/10131/0001195935c93610-0eb4-4bdc-b313-b46b49e79e6f
名前 / ファイル | ライセンス | アクション |
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yamanashi_P.pdf (1.5 MB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2018-08-20 | |||||
タイトル | ||||||
タイトル | Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Yamanashi, Yuki
× Yamanashi, Yuki× Nakaishi, Sotaro× Sugiyama, Akira× Takeuchi, Naoki× Yoshikawa, Nobuyuki |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Institute of Advanced Sciences, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π-shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π-shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π-shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and -shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0-π Josephson junctions. | |||||
書誌情報 |
Superconductor Science and Technology 巻 31, 号 10, p. 105003-1-105003-7, 発行日 2018-08-28 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 09532048 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10686810 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1088/1361-6668/aad78d | |||||
権利 | ||||||
権利情報 | © 2018 IOP Publishing Ltd. Original content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | IOP Publishing |