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{"_buckets": {"deposit": "2a53a0a5-b919-482a-8c09-84ea4de2f925"}, "_deposit": {"created_by": 3, "id": "8785", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "8785"}, "status": "published"}, "_oai": {"id": "oai:ynu.repo.nii.ac.jp:00008785", "sets": ["496"]}, "author_link": ["33478", "33479", "19078"], "item_2_biblio_info_8": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2016-06", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "6", "bibliographicPageEnd": "696", "bibliographicPageStart": "692", "bibliographicVolumeNumber": "E99-C", "bibliographic_titles": [{"bibliographic_title": "IEICE TRANSACTIONS on Electronics"}]}]}, "item_2_description_5": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.", "subitem_description_type": "Abstract"}]}, "item_2_publisher_35": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "The Institute of Electronics, Information and Communication Engineers"}]}, "item_2_relation_13": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "info:doi/10.1587/transele.E99.C.692", "subitem_relation_type_select": "DOI"}}]}, "item_2_relation_44": {"attribute_name": "関係URI", "attribute_value_mlt": [{"subitem_relation_name": [{"subitem_relation_name_text": "https://search.ieice.org/"}], "subitem_relation_type_id": {"subitem_relation_type_id_text": "https://search.ieice.org/", "subitem_relation_type_select": "URI"}}]}, "item_2_rights_14": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "copyright©2016 IEICE"}]}, "item_2_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "17451353", "subitem_source_identifier_type": "ISSN"}]}, "item_2_text_4": {"attribute_name": "著者所属", "attribute_value_mlt": [{"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}]}, "item_2_version_type_18": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Yamanashi, Yuki"}], "nameIdentifiers": [{"nameIdentifier": "19078", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "70467059", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]}, {"creatorNames": [{"creatorName": "Nishimoto, Shohei"}], "nameIdentifiers": [{"nameIdentifier": "33478", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yoshikawa, Nobuyuki"}], "nameIdentifiers": [{"nameIdentifier": "33479", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2018-01-24"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "Yamanashi2016IEICE.pdf", "filesize": [{"value": "1.6 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 1600000.0, "url": {"label": "Yamanashi2016IEICE.pdf", "url": "https://ynu.repo.nii.ac.jp/record/8785/files/Yamanashi2016IEICE.pdf"}, "version_id": "51556861-5104-494d-92a1-276f4b16428c"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates"}]}, "item_type_id": "2", "owner": "3", "path": ["496"], "permalink_uri": "http://hdl.handle.net/10131/00011459", "pubdate": {"attribute_name": "公開日", "attribute_value": "2018-01-24"}, "publish_date": "2018-01-24", "publish_status": "0", "recid": "8785", "relation": {}, "relation_version_is_last": true, "title": ["30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates"], "weko_shared_id": 3}
30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates
http://hdl.handle.net/10131/00011459
http://hdl.handle.net/10131/00011459c8df066e-a958-4d5a-9b70-02ad107aa0ad
名前 / ファイル | ライセンス | アクション |
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Yamanashi2016IEICE.pdf (1.6 MB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2018-01-24 | |||||
タイトル | ||||||
タイトル | 30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Yamanashi, Yuki
× Yamanashi, Yuki× Nishimoto, Shohei× Yoshikawa, Nobuyuki |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz. | |||||
書誌情報 |
IEICE TRANSACTIONS on Electronics 巻 E99-C, 号 6, p. 692-696, 発行日 2016-06 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 17451353 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1587/transele.E99.C.692 | |||||
権利 | ||||||
権利情報 | copyright©2016 IEICE | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | The Institute of Electronics, Information and Communication Engineers | |||||
関係URI | ||||||
識別子タイプ | URI | |||||
関連識別子 | https://search.ieice.org/ | |||||
関連名称 | https://search.ieice.org/ |