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Design and Implementation of a Fully Asynchronous SFQ Microprocessor: SCRAM2
http://hdl.handle.net/10131/4241
http://hdl.handle.net/10131/42412e816276-1b76-4b4f-99cf-f6ecbd317754
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
16_IEEE_2007_Nobumori.pdf (1.1 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||||||||||||
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| 公開日 | 2009-12-11 | |||||||||||||||||||
| タイトル | ||||||||||||||||||||
| タイトル | Design and Implementation of a Fully Asynchronous SFQ Microprocessor: SCRAM2 | |||||||||||||||||||
| 言語 | en | |||||||||||||||||||
| 言語 | ||||||||||||||||||||
| 言語 | eng | |||||||||||||||||||
| キーワード | ||||||||||||||||||||
| 主題 | asynchronous logic circuits, Separator, Gas channel, Water management, Slanted microgrooves, LIF method(en) | |||||||||||||||||||
| 資源タイプ | ||||||||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||||||||
| 資源タイプ | journal article | |||||||||||||||||||
| アクセス権 | ||||||||||||||||||||
| アクセス権 | open access | |||||||||||||||||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||||||||||||||||
| 著者 |
Nobumori, Y.
× Nobumori, Y.
× Nishigai, T.
× Nakamiya, K.
× Yoshikawa, N.
× Fujimaki, A.
× Terai, H.
× Yorozu, S.
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| 抄録 | ||||||||||||||||||||
| 内容記述タイプ | Abstract | |||||||||||||||||||
| 内容記述 | A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapid-single-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1 alpha. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA/cm(2) Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed. | |||||||||||||||||||
| 言語 | en | |||||||||||||||||||
| bibliographic_information |
en : IEEE transactions on applied superconductivity 巻 17, 号 2, Part 1, p. 478-481, ページ数 4, 発行日 2007-06 |
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| item_2_source_id_9 | ||||||||||||||||||||
| 収録物識別子タイプ | PISSN | |||||||||||||||||||
| 収録物識別子 | 10518223 | |||||||||||||||||||
| item_2_source_id_11 | ||||||||||||||||||||
| 収録物識別子タイプ | NCID | |||||||||||||||||||
| 収録物識別子 | AA10791666 | |||||||||||||||||||
| item_2_relation_13 | ||||||||||||||||||||
| 関連タイプ | isIdenticalTo | |||||||||||||||||||
| 識別子タイプ | DOI | |||||||||||||||||||
| 関連識別子 | 10.1109/TASC.2007.898658 | |||||||||||||||||||
| 権利 | ||||||||||||||||||||
| 言語 | en | |||||||||||||||||||
| 権利情報 | ©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||||||||||||||||
| 出版タイプ | ||||||||||||||||||||
| 出版タイプ | VoR | |||||||||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||||||||||
| 出版者 | ||||||||||||||||||||
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) | |||||||||||||||||||
