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An Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Using Delay-Line Clocking
http://hdl.handle.net/10131/00015240
http://hdl.handle.net/10131/00015240b7c55e14-8f1b-4d14-874d-8ce21c11a755
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
Yamae_IEEE_TAS_2023.pdf (605.1 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2023-01-25 | |||||
| タイトル | ||||||
| タイトル | An Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Using Delay-Line Clocking | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Junctions | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Logic gates | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Adders | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Energy dissipation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Delay lines | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Superconducting logic circuits | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Low latency communication | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | adders | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | delay lines | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | logic gates | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | parametric oscillators | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | superconducting logic circuits | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | synchronisation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | adiabatic quantum-flux-parametron logic | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | adiabatic quantum-flux-parametron ripple carry adder | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | adiabatic switching | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | AQFP logic gates | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | AQFP ripple | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | delay-line clocking | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | energy dissipation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | large-scale AQFP circuits | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | phase skipping operation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | phase synchronization | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | superconductor logic family | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | time 960.0 ps | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | word length 8 bit | |||||
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| 主題Scheme | Other | |||||
| 主題 | Adiabatic logic | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | low-latency clocking scheme | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | quantum flux parametron (QFP) | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | ripple carry adder | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Taiki, Yamae
× Taiki, Yamae× Naoki, Takeuchi× Nobuyuki, Yoshikawa |
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| 著者所属 | ||||||
| 値 | Department of Electrical and Computer Engineering, Yokohama National University & Research Fellow of Japan Society for the Promotion of Science | |||||
| 著者所属 | ||||||
| 値 | Research Center for Emerging Computing Technologies, the National Institute of Advanced Industrial Science and Technology | |||||
| 著者所属 | ||||||
| 値 | Department of Electrical and Computer Engineering, Yokohama National University & Institute of Advanced Sciences, Yokohama National University | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation. | |||||
| 書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 33, 号 5, 発行日 2023-01-25 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 15582515 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10791666 | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | info:doi/10.1109/TASC.2023.3239833 | |||||
| 権利 | ||||||
| 権利情報 | © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 出版者 | ||||||
| 出版者 | Institute of Electrical and Electronics Engineers | |||||
| 関係URI | ||||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/TASC.2023.3239833 | |||||
| 関連名称 | https://doi.org/10.1109/TASC.2023.3239833 | |||||
