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Design of Binary Convolution Operation Circuit for Binarized Neural Networks Using Single-Flux-Quantum Circuit
http://hdl.handle.net/10131/00014245
http://hdl.handle.net/10131/000142458b41111a-f01e-4ee5-b481-209f55c956dd
名前 / ファイル | ライセンス | アクション |
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Li2022IEEE.pdf (668.4 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2022-02-08 | |||||
タイトル | ||||||
タイトル | Design of Binary Convolution Operation Circuit for Binarized Neural Networks Using Single-Flux-Quantum Circuit | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Convolution, Logic gates, Kernel, Pipelines, Power demand, Hardware, Pipeline processing, Single-flux-quantum (SFQ) circuit, binary convolution, superconducting integrated circuit | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Zongyuan, Li
× Zongyuan, Li× Yuki Yamanashi× Nobuyuki Yoshikawa |
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著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We design a binary convolution operation circuit (BCOC) using a single-flux-quantum circuit for high-speed and energy-efficient neural network. The proposed circuit is used for binary convolution operations using a convolution kernel size of 3 × 3, which accelerates the forward propagation process of a binary neural network (BNN). We analyze the binary convolution process and propose a bisection method for optimization. The BCOC is designed with a gate-level pipeline architecture and uses the bisection method for reduced number of pipeline stages. Thus, the circuit area of the BCOC is reduced by approximately 50% compared with that of a BCOC without the bisection method. We design the BCOC with 3270 Josephson junctions using a 10 kA/cm^2 Nb process. The measurement results show that the BCOC can perform binary convolution operations with a kernel size of 3 × 3. Compared to a CMOS circuit, BCOC increases the power efficiency by 3.9 times. In future research, we will build up a library of BNNs based on SFQ circuits to simulate various BNN structures. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 32, 号 4, p. 1300305, 発行日 2022-01-04 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 10518223 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11946236 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2022.3140286 | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | IEEE | |||||
関係URI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/TASC.2022.3140286 | |||||
関連名称 | https://doi.org/10.1109/TASC.2022.3140286 |