WEKO3
アイテム
{"_buckets": {"deposit": "aef0c927-cfcc-4738-b759-734712938031"}, "_deposit": {"created_by": 3, "id": "10965", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "10965"}, "status": "published"}, "_oai": {"id": "oai:ynu.repo.nii.ac.jp:00010965", "sets": ["496"]}, "author_link": ["35237", "19078", "38452"], "item_2_biblio_info_8": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2021-01-08", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "3", "bibliographicPageStart": "1300406", "bibliographicVolumeNumber": "31", "bibliographic_titles": [{"bibliographic_title": "IEEE Transactions on Applied Superconductivity"}]}]}, "item_2_description_5": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "We investigated the hardware implementation of an area-efficient superconducting lookup table (LUT) based on a single flux quantum (SFQ) logic by using a newly proposed small memory cell. The memory cell is composed of a nondestructive read-out (NDRO) flip-flop with input circuits that convert the input dc current to an SFQ pulse signal. The datum can be written to the selected memory cell in the 2-D memory cell array by applying both x- and y-directional dc control currents. The data stored in the memory cell array can be reset simultaneously by applying a dc current to a common reset line. By employing the new memory cell, wiring for reconfiguring the data and resetting the memory cell array can be drastically simplified compared to that of the conventional SFQ LUT. We implemented and tested the memory cell and confirmed the correct operation with wide dc bias and input-current margins. We designed the 16-b LUT using the designed memory cells. The circuit area and the number of Josephson junctions of the 16-b LUT is reduced by approximately 24 and 41%, respectively, compared to those of the LUT based on the conventional architecture. We experimentally obtained the correct operation and reconfiguration of the 4-b LUT that uses the new memory cells with a normalized bias margin of -22 to +7%.", "subitem_description_type": "Abstract"}]}, "item_2_publisher_35": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_2_relation_13": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "info:doi/10.1109/TASC.2021.3049771", "subitem_relation_type_select": "DOI"}}]}, "item_2_relation_44": {"attribute_name": "関係URI", "attribute_value_mlt": [{"subitem_relation_name": [{"subitem_relation_name_text": "https://doi.org/10.1109/TASC.2021.3049771"}], "subitem_relation_type_id": {"subitem_relation_type_id_text": "https://doi.org/10.1109/TASC.2021.3049771", "subitem_relation_type_select": "DOI"}}]}, "item_2_source_id_11": {"attribute_name": "書誌レコードID", "attribute_value_mlt": [{"subitem_source_identifier": "AA11946236", "subitem_source_identifier_type": "NCID"}]}, "item_2_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "10518223", "subitem_source_identifier_type": "ISSN"}]}, "item_2_text_4": {"attribute_name": "著者所属", "attribute_value_mlt": [{"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}, {"subitem_text_value": "Department of Electrical and Computer Engineering, Yokohama National University"}]}, "item_2_version_type_18": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Takuya, Hosoya"}], "nameIdentifiers": [{"nameIdentifier": "38452", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yuki, Yamanashi"}], "nameIdentifiers": [{"nameIdentifier": "19078", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "70467059", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=70467059"}]}, {"creatorNames": [{"creatorName": "Nobuyuki, Yoshikawa"}], "nameIdentifiers": [{"nameIdentifier": "35237", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "70202398", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=70202398"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2021-03-01"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "09316703.pdf", "filesize": [{"value": "4.0 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 4000000.0, "url": {"label": "09316703.pdf", "url": "https://ynu.repo.nii.ac.jp/record/10965/files/09316703.pdf"}, "version_id": "a21dcaeb-f399-4d34-99d1-48aae73d2116"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "Computer architecture", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Microprocessors", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Table lookup", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Wiring", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Current measurement", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Magnetic tunneling", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Decoding", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Cryogenic memory", "subitem_subject_scheme": "Other"}, {"subitem_subject": "lookup table (LUT)", "subitem_subject_scheme": "Other"}, {"subitem_subject": "memory cell", "subitem_subject_scheme": "Other"}, {"subitem_subject": "single flux quantum (SFQ) circuit", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents"}]}, "item_type_id": "2", "owner": "3", "path": ["496"], "permalink_uri": "http://hdl.handle.net/10131/00013624", "pubdate": {"attribute_name": "公開日", "attribute_value": "2021-03-01"}, "publish_date": "2021-03-01", "publish_status": "0", "recid": "10965", "relation": {}, "relation_version_is_last": true, "title": ["Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents"], "weko_shared_id": -1}
Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents
http://hdl.handle.net/10131/00013624
http://hdl.handle.net/10131/0001362491d14b3a-8311-4e67-a625-49b925a5bfb3
名前 / ファイル | ライセンス | アクション |
---|---|---|
09316703.pdf (4.0 MB)
|
|
Item type | 学術雑誌論文 / Journal Article(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2021-03-01 | |||||
タイトル | ||||||
タイトル | Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | Computer architecture, Microprocessors, Table lookup, Wiring, Current measurement, Magnetic tunneling, Decoding, Cryogenic memory, lookup table (LUT), memory cell, single flux quantum (SFQ) circuit | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Takuya, Hosoya
× Takuya, Hosoya× Yuki, Yamanashi× Nobuyuki, Yoshikawa |
|||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
著者所属 | ||||||
Department of Electrical and Computer Engineering, Yokohama National University | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We investigated the hardware implementation of an area-efficient superconducting lookup table (LUT) based on a single flux quantum (SFQ) logic by using a newly proposed small memory cell. The memory cell is composed of a nondestructive read-out (NDRO) flip-flop with input circuits that convert the input dc current to an SFQ pulse signal. The datum can be written to the selected memory cell in the 2-D memory cell array by applying both x- and y-directional dc control currents. The data stored in the memory cell array can be reset simultaneously by applying a dc current to a common reset line. By employing the new memory cell, wiring for reconfiguring the data and resetting the memory cell array can be drastically simplified compared to that of the conventional SFQ LUT. We implemented and tested the memory cell and confirmed the correct operation with wide dc bias and input-current margins. We designed the 16-b LUT using the designed memory cells. The circuit area and the number of Josephson junctions of the 16-b LUT is reduced by approximately 24 and 41%, respectively, compared to those of the LUT based on the conventional architecture. We experimentally obtained the correct operation and reconfiguration of the 4-b LUT that uses the new memory cells with a normalized bias margin of -22 to +7%. | |||||
書誌情報 |
IEEE Transactions on Applied Superconductivity 巻 31, 号 3, p. 1300406, 発行日 2021-01-08 |
|||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 10518223 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11946236 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | info:doi/10.1109/TASC.2021.3049771 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | IEEE | |||||
関係URI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/TASC.2021.3049771 | |||||
関連名称 | https://doi.org/10.1109/TASC.2021.3049771 |